9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y= a|b;// write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y= ~a;// write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    wire w1,w2, w3,w4;
    not_gate abar (a, w1);
    not_gate bbar (b, w2);// TODO: declare intermediate wires
    and_gate a1(a, w2, w3);
    and_gate a2(w1, b, w4);
    or_gate or1(w3, w4, y);
    // TODO: instantiate required gates

endmodule