9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
wire aandnotb, notb, bandnota, nota;
    // TODO: instantiate required gates
not_gate nota1(.a(a), .y(nota));
not_gate notb1(.a(b), .y(notb));
and_gate and1 (.a(a),.b(notb),.y(aandnotb));
and_gate and2 (.a(b),.b(nota),.y(bamdnota));
or_gate result (.a(bamdnota),.b(aandnotb),.y(y));
endmodule