9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire na, nb, axnb, naxb;

    // TODO: instantiate required gates
    not_gate N0(a, na), N1(b, nb);
    and_gate AND0(a, nb, axnb), AND1(na, b, naxb);
    or_gate OR0(axnb, naxb, y);

endmodule