9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire b_not, a_not;
    wire xor_in_1, xor_in_2;

    // TODO: instantiate required gates
    not_gate n1 (.a(a), .y(a_not));
    not_gate n2 (.a(b), .y(b_not));

    and_gate a1 (.a(a), .b(b_not), .y(xor_in_1));
    and_gate a2 (.a(b), .b(a_not), .y(xor_in_2));

    or_gate o1 (.a(xor_in_1), .b(xor_in_2), .y(y));
endmodule