9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    // TODO: instantiate required gates

wire w1,w2,w3,w4;

not n1 (w1,b);
not n2 (w2,a);

and a1 (w3,a,w1);
and a2 (w4,w2,b);

or o1 (y,w3,w4);



endmodule