How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a | b;
endmodule
module not_gate(input a, output y);
assign y= ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire w0,w1,w2,w3;
not_gate ng1(
.a(a),
.y(w0)
);
not_gate ng2(
.a(b),
.y(w1)
);
and_gate ag1(
.a(a),
.b(w1),
.y(w3)
);
and_gate ag2(
.a(w0),
.b(b),
.y(w4)
);
or_gate og(
.a(w3),
.b(w4),
.y(y)
);
endmodule