9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire [3:0] wires;
    // TODO: instantiate required gates

    and_gate a0(.a(a), .b(wires[0]), .y(wires[1]));
    and_gate a1(.a(b), .b(wires[2]), .y(wires[3]));

    not_gate n0(.a(b), .y(wires[0]));
    not_gate n1(.a(a), .y(wires[2]));

    or_gate o0(.a(wires[1]), .b(wires[3]), .y(y));
endmodule