9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
        assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    
    // TODO: declare intermediate wires
        wire out_and1;
        wire out_and2;
        wire out_not1;
        wire out_not2;
    // TODO: instantiate required gates

    not_gate u_not_gate_1 (
        .a(a),
        .y(out_not1)
    );

     not_gate u_not_gate_2 (
        .a(b),
        .y(out_not2)
    );

    and_gate u_and_gate_1 (
        .a(a),
        .b(out_not2),
        .y(out_and1)
    );

    and_gate u_and_gate_2 (
        .a(out_not1),
        .b(b),
        .y(out_and2)
    );

    or_gate u_or_gate (
        .a(out_and1),
        .b(out_and2),
        .y(y)
    );


endmodule