// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y=a|b;
endmodule
module not_gate(input a, output y);
assign y=~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire p1,p2;
wire n1,n2;
not_gate NA(a,n1);
not_gate NB(b,n2);
and_gate a1(a,n2,p1);
and_gate s2(n1,b,p2);
or_gate o1(p1,p2,y);
endmodule