9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire na, nb, anb, nab; 

    // TODO: instantiate required gates
    not_gate not0(.a(a),.y(na));
    not_gate not1(.a(b),.y(nb));

    and_gate and0(.a(a),.b(nb),.y(anb));
    and_gate and1(.a(na),.b(b),.y(nab));

    or_gate or0(.a(anb),.b(nab),.y(y));

endmodule