9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign  y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire not_a, not_b, t1, t2;
    // TODO: instantiate required gates
    not_gate not1(.a(a), .y(not_a));
    not_gate not2(.a(b), .y(not_b));
    and_gate and1(.a(a), .b(not_b), .y(t1));
    and_gate and2(.a(not_a), .b(b), .y(t2));
    or_gate or1(.a(t1), .b(t2), .y(y));
endmodule