9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w1;
    wire w2;
    wire w3;
    wire w4;
    // TODO: instantiate required gates
    not_gate a1 (a, w1);
    not_gate a2 (b, w2);

    and_gate b1 (a, w2, w3);
    and_gate b2 (b, w1, w4);

    or_gate c1 (w3, w4, y);

endmodule