9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
wire bbar,y1,abar,y2;
    // TODO: declare intermediate wires
    not_gate n1(.a(b),.y(bbar));

    and_gate a1(.a(a),.b(bbar),.y(y1));
    not_gate n2(.a(a),.y(abar));
    and_gate a2(.a(abar),.b(b),.y(y2));
    or_gate o1(.a(y1),.b(y2),.y(y));

    // TODO: instantiate required gates

endmodule