9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y= a | b;
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y=~a;
    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    wire wa, wb, w1, w2;
    not_gate n1(a,wa);
    not_gate n2(.a(b),.y(wb));
    and_gate a1(.a(a),.b(wb),.y(w1));
    and_gate a2(.a(wa),.b(b),.y(w2));
    or_gate o1(.a(w1),.b(w2),.y(y));


    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule