9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
assign y = a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
// assign w1,w2,w3,w4;
// assign w1 = ~b;
// assign w2 = ~a;
// assign w3 = a&w1;
// assign w4 = b&w2;
// assign y = w3|w4;

    // TODO: instantiate required gates
wire w1,w2,w3,w4;
not_gate n1(.a(a), .y(w1));
not_gate n2(.a(b), .y(w2));
and_gate n3(.a(a), .b(w2), .y(w3));
and_gate n4(.a(b), .b(w1), .y(w4));
or_gate n5(.a(w3), .b(w4), .y(y));

endmodule