// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y=a|b;
endmodule
module not_gate(input a, output y);
assign y=~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire ab,bb,f1,f2;
not_gate n1(b,bb);
and_gate a1(a,bb,f1);
not_gate n2(a,ab);
and_gate a2(ab,b,f2);
or_gate o1(f1,f2,y);
endmodule