// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y=a|b;
endmodule
module not_gate(input a, output y);
assign y=~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire w1,w2,w3,w4;
not_gate n1(a,w1);
not_gate n2(b,w2);
and_gate a1(a,w2,w3);
and_gate a2(w1,b,w4);
or_gate o1(w3,w4,y);
endmodule