9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a|b;

endmodule

module not_gate(input a, output y);
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    
    wire and_out_1,and_out_2, not_a,not_b;
    not_gate not_1(.a(a), .y(not_a));
    not_gate not_2(.a(b), .y(not_b));
    and_gate and_1 (.a(not_a),.b(b), .y(and_out_1));
    and_gate and_2 (.a(a),.b(not_b), .y(and_out_2));
    or_gate o1(.a(and_out_1),.b(and_out_2),.y(y));

    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule