How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a | b;// write code here for or gate
endmodule
module not_gate(input a, output y);
assign y = ~a; // write code here for not gate
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire w1,w2,w3,w4;
not_gate n1(b,w1);
not_gate n2(a,w2);
and_gate n3(a,w1,w3);
and_gate n4(b,w2,w4);
or_gate n5(w3,w4,y);
endmodule