9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
assign y=a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y=~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
wire w1,w2,n1,n2;
not_gate not1(b,n1);
not_gate not2(a,n2);
and_gate a1(a,n1,w1);
and_gate a2(b,n2,w2);
or_gate o1 (w1,w2,y);

    // TODO: instantiate required gates

endmodule