9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
assign y= a | b;
    // write code here for or gate

endmodule

module not_gate(input a, output y);
assign y = ~a;
    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
wire and1, and2;

and_gate a1(.a(a), .b(~b), .y(and1));
and_gate a2(.a(~a), .b(b),.y(and2));
or_gate o1(.a(and1), .b(and2), .y(y));

    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule