9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a ;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire o1,o2,n1,n2;

    // TODO: instantiate required gates
    and_gate a11(
        .a(a),
        .b(n2),
        .y(o1)
    );
    and_gate a21(
        .a(n1),
        .b(b),
        .y(o2)
    );
    or_gate o11(
        .a(o1),
        .b(o2),
        .y(y)
    );
    not_gate n11(
        .a(a),
        .y(n1)
    );
    not_gate n21(
        .a(b),
        .y(n2)
    );

endmodule