9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a||b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign a=~y;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire or1,or2,n1,n2;
    // TODO: instantiate required 
    
    and_gate truc1(.a(a), .b(~b), .y(or1));
    and_gate truc2(.a(~a), .b(b), .y(or2));

    or_gate truc3(.a(or1), .b(or2), .y(y));


endmodule