9. XOR Gate Using Basic Gates

How do you plan to solve it?

module xor_gate(input a,b,output y);

wire w1,w2,w3,w4;
not n1(w1,b);
not n2(w2,a);
and a1(w3, a,w1);
and a2(w4,w2,b);
or o1(y,w3,w4);

endmodule