9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    wire nota, notb;
    wire w1, w2;

    // NOT gates
    not_gate n1 (a, nota);   // nota = ~a
    not_gate n2 (b, notb);   // notb = ~b

    // AND gates
    and_gate a1 (a, notb, w1);   // w1 = a & ~b
    and_gate a2 (nota, b, w2);   // w2 = ~a & b

    // OR gate
    or_gate  o1 (w1, w2, y);     // y = w1 | w2
 

    // TODO: instantiate required gates

endmodule