9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota,notb,out1,out2;
    not_gate ob1(a,nota);
    not_gate ob2(b,notb);
    and_gate ob3(nota,b,out1);
    and_gate ob4(a,notb,out2);
    or_gate ob5(out1,out2,y);
    // TODO: instantiate required gates

endmodule