9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y=a|b; // write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y=~a;// write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
   wire w1,w2;
    // TODO: declare intermediate wires

  and G1(w1,a,~b), G2(w2,~a,b);
  or G3(y,w1,w2);  // TODO: instantiate required gates

endmodule