9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
assign y = a |b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w1,w2;
    // TODO: instantiate required gates
    and_gate a1 (a,~b,w1);
    and_gate a2 (~a,b,w2);
    or_gate a3 (w1,w2,y);

endmodule