9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;    // OR gate implementation
endmodule

module not_gate(input a, output y);
    assign y = ~a;       // NOT gate implementation
endmodule

// ============================================================
// XOR Gate
// ============================================================
// Equation: y = (a & b') | (a' & b)
module xor_gate (
    input  a, b,
    output y
);
    // declare intermediate wires
    wire nota, notb;
    wire and1_out, and2_out;

    // instantiate required gates
    not_gate u1(.a(a), .y(nota));       // nota = ~a
    not_gate u2(.a(b), .y(notb));       // notb = ~b

    and_gate u3(.a(a), .b(notb), .y(and1_out));   // and1_out = a & ~b
    and_gate u4(.a(nota), .b(b), .y(and2_out));   // and2_out = ~a & b

    or_gate  u5(.a(and1_out), .b(and2_out), .y(y));  // y = (a & ~b) | (~a & b)
endmodule