9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y=a | b;
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y=!a;
    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
     not_gate not1(.a(b),.y(w1));
     not_gate not2(.a(a),.y(w2));
     and_gate and1 (.a(a),.b(w1),.y(a1));
     and_gate and2 (.a(w2),.b(b),.y(a2));
     or_gate or1(.a(a1),.b(a2),.y(y));
     
     
    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule