9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire anot, bnot, abnot, anotb;
    // TODO: instantiate required gates
    not_gate n1(.a(a), .y(anot));
    not_gate n2(.a(b), .y(bnot));

    and_gate a1(.a(a),.b(bnot),.y(abnot));
    and_gate a2(.a(anot),.b(b),.y(anotb));

    or_gate o1(.a(anotb),.b(abnot),.y(y));

endmodule