How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y=a|b;
endmodule
module not_gate(input a, output y);
assign y=~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire w0,w1,w2,w3;
not_gate n0(
.a(a),
.y(w1)
);
not_gate n1(
.a(b),
.y(w2)
);
and_gate a0(
.a(a),
.b(w2),
.y(w3)
);
and_gate a1(
.a(w1),
.b(b),
.y(w4)
);
or_gate o0(
.a(w4),
.b(w3),
.y(y)
);
endmodule