9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire p,q,r,s;
    // TODO: instantiate required gates
    not_gate not1 (.a(b),.y(p));
    and_gate and1 (.a(a),.b(p),.y(r));
    not_gate not2 (.a(a),.y(q));
    and_gate and2 (.a(b),.b(q),.y(s));
    or_gate or1 (.a(r),.b(s),.y(y));

endmodule