9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire a1,b1,d1,d2;
    not_gate u1(
        .a(a),
        .y(a1)
    );
    not_gate u2(
        .a(b),
        .y(b1)
    );
    
    and_gate u3(
        .a(a),
        .b(b1),
        .y(d1)
    );
    and_gate u4(
        .a(a1),
        .b(b),
        .y(d2)
    );
    or_gate u5(
        .a(d1),
        .b(d2),
        .y(y)
    );

    // TODO: instantiate required gates

endmodule