9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
  assign y=a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y=~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
wire not_a,not_b;
wire w1,w2;
not_gate n1(a,not_a);
not_gate n2(b,not_b);
and_gate a1(a,not_b,w1);
and_gate a2(b,not_a,w2);
or_gate o1(w1,w2,y);// TODO: declare intermediate wires

         // TODO: instantiate required gates
endmodule