9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire a_bar, b_bar, w1, w2;


    // TODO: instantiate required gates
    not_gate n1 (a , a_bar);
    not_gate n2 (b , b_bar);
    and_gate a1 (a, b_bar, w1);
    and_gate a2 (a_bar, b, w2);
    or_gate o1 (w1, w2, y);

endmodule