9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire a_bar,b_bar, y0, y1;

    // TODO: instantiate required gates
    and_gate DUT0(.a(a), .b(b_bar), .y(y0));
    and_gate DUT1(.a(a_bar), .b(b), .y(y1));
    or_gate DUT2(.a(y0), .b(y1), .y(y));
    not_gate DUT3(.a(a), .y(a_bar));
    not_gate DUT4(.a(b), .y(b_bar));


endmodule