How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a | b;
endmodule
module not_gate(input a, output y);
assign y = ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire w1,w2;
not_gate not_gate1(.a(a),.y(nota));
not_gate not_gate2(.a(b),.y(notb));
and_gate and_gate1(.a(a),.b(notb),.y(andout1));
and_gate and_gate2(.a(b),.b(nota),.y(andout2));
or_gate or_gate1(.a(andout1),.b(andout2),.y(y));
endmodule