9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a ;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire [3:0]w ;
    // TODO: instantiate required gates
    not_gate A(.y(w[0]), .a(a));
    not_gate B(.y(w[1]), .a(b));

    and_gate A1(.y(w[2]), .a(a) ,.b(w[1]));
    and_gate A2(.y(w[3]), .a(b), .b(w[0]));

    or_gate OR(.y(y), .a(w[2]) ,.b(w[3]));

endmodule