9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~ a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire not_a,not_b,a_and_b_bar,a_bar_and_b;

    // TODO: instantiate required gates
    not_gate not_gate_a(a,not_a);
    not_gate not_gate_b(b,not_b);
    and_gate and_gate_a_and_b_bar(a,not_b,a_and_b_bar);
    and_gate and_gate_a_bar_and_b(not_a,b,a_bar_and_b);
    or_gate or_a_and_b_bar_or_a_bar_and_b(a_and_b_bar,a_bar_and_b,y);

endmodule