9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y = a | b;

endmodule

module not_gate(input a, output y);
    assign a = ~a;

   

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w1,w2;

    // TODO: instantiate required gates
    assign w1 = ( a  & ~(b));
    assign w2 = ( ~(a)  & b);
    assign y = w1 | w2;
    
endmodule