9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    wire c,d,e,f;
    not_gate notb(.a(b),.y(c));
    not_gate nota(.a(a),.y(d));
    and_gate and1(.a(a),.b(c),.y(e));
    and_gate and2(.a(d),.b(b),.y(f));
    or_gate or1(.a(e),.b(f),.y(y));

    // TODO: instantiate required gates

endmodule