9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w_inv0;
    wire w_inv1;
    wire w_and0;
    wire w_and1;

    // TODO: instantiate required gates
    not_gate U_INV0(.a (a), .y (w_inv0));
    not_gate U_INV1(.a (b), .y (w_inv1));
    and_gate U_AND0(.a (a), .b (w_inv1), .y (w_and0));
    and_gate U_AND1(.a (w_inv0), .b (b), .y (w_and1));
    or_gate  U_OR0(.a (w_and0), .b (w_and1), .y (y));

endmodule