9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~ a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    not_gate nota1 (.a(b),.y(w1));
    and_gate and1  (.a(a),.b(w1),.y(z1));
    not_gate nota2 (.a(a), .y(w2));
    and_gate and2 (.a(b), .b(w2), .y(z2));
    or_gate or1 (.a(z1), .b(z2), .y(y));
    // TODO: instantiate required gates

endmodule