How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y=a|b;
endmodule
module not_gate(input a, output y);
assign y = ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire not_b,not_a,and1_out,and2_out;
not_gate g1(b,not_b);
not_gate g0(a,not_a);
and_gate g2(a,not_b,and1_out);
and_gate g3(not_a,b,and2_out);
or_gate g4(and1_out,and2_out,y);
endmodule