9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire skibidi1, skibidi2;
    wire daoa, daob;
    // TODO: instantiate required gates
    not_gate dao1(.a(a),.y(daoa));
    not_gate dao2(.a(b),.y(daob));
    and_gate var1(.a(a),.b(daob),.y(skibidi1));
    and_gate var2(.a(daoa),.b(b),.y(skibidi2));
    or_gate ketqua(.a(skibidi1),.b(skibidi2),.y(y));
endmodule