9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y =  a | b;
endmodule

module not_gate(input a, output y);
   assign y = !a; // not inverter
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    wire a_inv, b_inv;

    // a inverter
    not_gate a0 (
        .a(a),
        .y(a_inv)
    );

    // b inverter
    not_gate b0 (
        .a(b),
        .y(b_inv)
    );

    wire and_1, and_2;

    and_gate a1(
        .a(a),
        .b(b_inv),
        .y(and_1)
    );

    and_gate b1(
        .a(a_inv),
        .b(b),
        .y(and_2)
    );

    or_gate c1(
        .a(and_1),
        .b(and_2),
        .y(y)
    );

endmodule