9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire nota, notb, w0, w1;
    // TODO: instantiate required gates
    not_gate lol(
        .a(a),
        .y(nota)
    );

    not_gate lel(
        .a(b),
        .y(notb)
    );

    and_gate lil(
        .a(a),
        .b(notb),
        .y(w0)
    );

    and_gate lul(
        .a(nota),
        .b(b),
        .y(w1)
    );

    or_gate lal(
        .a(w0),
        .b(w1),
        .y(y)
    );
endmodule