9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;


endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y= ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
   wire bbar,abar,abbar,abarb;

    // TODO: instantiate required gates
    not_gate Abar(.a(a),.y(abar));
    not_gate Bbar(.a(b),.y(bbar));
    and_gate Abbar(.a(a),.b(bbar),.y(abbar));
    and_gate Bbbar(.a(abar),.b(b),.y(abarb));
    or_gate Out(.a(abarb),.b(abbar),.y(y));

endmodule