9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire na, nb, anb, nab;

    // TODO: instantiate required gates
    not_gate nota(a, na);
    not_gate notb(b, nb);
    and_gate anotb(a, nb, anb);
    and_gate notab(na, b, nab);
    or_gate y_out(anb, nab, y);
endmodule